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EP7312 Data Sheet
FEATURES
I ARM(R)720T Processor -- ARM7TDMI CPU operating at speeds of 74 and 90 MHz -- 8 KBytes of four-way set-associative cache -- MMU with 64-entry TLB -- Thumb code support enabled I Ultra low power -- 90 mW at 74 MHz typical -- 108 mW at 90 MHz typical -- <.03 mW in the Standby State I Advanced audio decoder/decompression capability -- Supports bit streams with adaptive bit rates -- Allows for support of multiple audio decompression algorithms (MP3, WMA, AAC, Audible, etc.)
High-Performance, Low-Power System on Chip with SDRAM and Enhanced Digital Audio Interface
OVERVIEW
The Cirrus LogicTM EP7312 is designed for ultra-lowpower portable and line-powered applications such as portable consumer entertainment devices, home and car audio juke box systems, and general purpose industrial control applications, or any device that features the added capability of digital audio compression & decompression. The core-logic functionality of the device is built around an ARM720T processor with 8 KBytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Microsoft(R) Windows(R) CE and Linux(R). (cont.)
(cont.)
BLOCK DIAGRAM
D ig ita l A u d io In terfa ce
E PB B us
C lo c ks & T im ers
SERIAL PORTS
S erial In terfa ce
P o w er M an ag em e n t
ARM720T
IC E -J T A G
A R M 7T D M I C P U C o re In terru p ts , P W M & G P IO
USER INTERFACE
(2) U A R T s w / IrD A
8 KB C ache
B oo t ROM
W rite B u ffe r
B us B rid g e
MMU
K e yp ad & T o u ch S cre en I/F
In tern al D a ta B u s M em o ry C o n tro lle r M a ve ric kK e y T M
S RAM I/F
S DRAM I/F
O n -c h ip S R A M 48 K B
LCD C o n tro lle r
MEMORY and STORAGE
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EP7312 High-Performance, Low-Power System on Chip
FEATURES (cont)
I 48 KBytes of on-chip SRAM I MaverickKey IDs -- 32-bit unique ID can be used for DRM compliance 128-bit random ID I Available in 74 and 90 MHz clock speeds I LCD controller -- Interfaces directly to a single-scan panel monochrome STN LCD -- Interfaces to a single-scan panel color STN LCD with minimal external glue logic I Full JTAG boundary scan and Embedded ICE support I Integrated Peripheral Interfaces -- 32-bit SDRAM Interface up to 2 external banks -- 8/32/16-bit SRAM/FLASH/ROM Interface -- Digital Audio Interface providing glueless interface to low-power DACs, ADCs and CODECs -- Two Synchronous Serial Interfaces (SSI1, SSI2) -- CODEC Sound Interface -- 8x8 Keypad Scanner
TM
-- 27 General Purpose Input/Output pins -- Dedicated LED flasher pin from the RTC I Internal Peripherals -- Two 16550 compatible UARTs -- IrDA Interface -- Two PWM Interfaces -- Real-time Clock -- Two general purpose 16-bit timers -- Interrupt Controller -- Boot ROM I Package -- 208-Pin LQFP -- 256-Ball PBGA -- 204-Ball TFBGA I The fully static EP7312 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process
OVERVIEW (cont.)
The EP7312 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V. The device has three basic power states: operating, idle and standby. MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, high quality ADCs, DACs, or CODECs such as the Cirrus Logic CS53L32A, CS43L42, and CS42L50 are easily added to an EP73xx design via the DAI. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Simply by adding desired memory and peripherals to the highly integrated EP7312 completes a low-power system solution. All necessary interface logic is integrated onchip.
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Table of Contents
FEATURES ...........................................................................................................................................1 OVERVIEW ...........................................................................................................................................1 FEATURES (cont) .......................................................................................................................................................2 OVERVIEW (cont.) ......................................................................................................................................................2 Description of the EP7312's Components, Functionality, and Interfaces ....................................6
Processor Core - ARM720T ..................................................................................................................................6 Power Management ..............................................................................................................................................6 MaverickKeyTM Unique ID ......................................................................................................................................6 Memory Interfaces .................................................................................................................................................6 Digital Audio Capability .........................................................................................................................................7 Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7 Digital Audio Interface (DAI) ..................................................................................................................................7 CODEC Interface ..................................................................................................................................................8 SSI2 Interface ........................................................................................................................................................8 Synchronous Serial Interface ................................................................................................................................8 LCD Controller .......................................................................................................................................................8 64-Key Keypad Interface .......................................................................................................................................9 Interrupt Controller ................................................................................................................................................9 Real-Time Clock ....................................................................................................................................................9 PLL and Clocking ..................................................................................................................................................9 DC-to-DC Converter Interface (PWM) ................................................................................................................. 10 Timers ................................................................................................................................................................. 10 General Purpose Input/Output (GPIO) ................................................................................................................ 10 Hardware Debug Interface .................................................................................................................................. 10 LED Flasher ........................................................................................................................................................ 10 Internal Boot ROM ...............................................................................................................................................10 Packaging ............................................................................................................................................................ 10 Pin Multiplexing ................................................................................................................................................... 11 System Design ....................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................13
Absolute Maximum Ratings .................................................................................................................................13 Recommended Operating Conditions ................................................................................................................. 13 DC Characteristics .............................................................................................................................................. 13
Timings ...............................................................................................................................................15
Timing Diagram Conventions .................................................................................................................... 15 Timing Conditions ...................................................................................................................................... 15 SDRAM Interface ................................................................................................................................................ 16 SDRAM Load Mode Register Cycle .......................................................................................................... 17 SDRAM Burst Read Cycle ......................................................................................................................... 18 SDRAM Burst Write Cycle ......................................................................................................................... 19 SDRAM Refresh Cycle .............................................................................................................................. 20 Static Memory ..................................................................................................................................................... 21 Static Memory Single Read Cycle ............................................................................................................. 22 Static Memory Single Write Cycle ............................................................................................................. 23 Static Memory Burst Read Cycle ............................................................................................................... 24 Static Memory Burst Write Cycle ............................................................................................................... 25 SSI1 Interface ...................................................................................................................................................... 26 SSI2 Interface ...................................................................................................................................................... 27 LCD Interface ...................................................................................................................................................... 28
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EP7312 High-Performance, Low-Power System on Chip
JTAG Interface .................................................................................................................................................... 29
Packages ............................................................................................................................................ 30
208-Pin LQFP Package Characteristics ............................................................................................................. 30
EP7312 208-Pin LQFP ............................................................................................................................ 30
208-Pin LQFP Pin Diagram ................................................................................................................................ 31
EP7312 ............................................................................................................................................... 31
208-Pin LQFP Numeric Pin Listing ..................................................................................................................... 32 204-Ball TFBGA Package Characteristics .......................................................................................................... 38 204-Ball TFBGA Pinout (Top View) ..................................................................................................................... 39 204-Ball TFBGA Ball Listing ............................................................................................................................... 40 256-Ball PBGA Package Characteristics ............................................................................................................ 46 256-Ball PBGA Pinout (Top View) ....................................................................................................................... 48 256-Ball PBGA Ball Listing ................................................................................................................................. 49 JTAG Boundary Scan Signal Ordering ............................................................................................................... 54
CONVENTIONS ................................................................................................................................. 60
Acronyms and Abbreviations .............................................................................................................................. 60 Units of Measurement ......................................................................................................................................... 60 General Conventions .......................................................................................................................................... 61 Pin Description Conventions ............................................................................................................................... 61
Ordering Information ........................................................................................................................ 62
Ordering Information Legend .............................................................................................................................. 62
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EP7312 High-Performance, Low-Power System on Chip
List of Figures
Figure 1. A Fully-Configured EP7312-Based System ................................................................................................... 12 Figure 2. Legend for Timing Diagrams ......................................................................................................................... 15 Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ............................................................................ 17 Figure 4. SDRAM Burst Read Cycle Timing Measurement .......................................................................................... 18 Figure 5. SDRAM Burst Write Cycle Timing Measurement .......................................................................................... 19 Figure 6. SDRAM Refresh Cycle Timing Measurement ................................................................................................ 20 Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22 Figure 8. Static Memory Single Write Cycle Timing Measurement ...............................................................................23 Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................ 24 Figure 10. Static Memory Burst Write Cycle Timing Measurement .............................................................................. 25 Figure 11. SSI1 Interface Timing Measurement ........................................................................................................... 26 Figure 12. SSI2 Interface Timing Measurement ........................................................................................................... 27 Figure 13. LCD Controller Timing Measurement .......................................................................................................... 28 Figure 14. JTAG Timing Measurement ......................................................................................................................... 29 Figure 15. 208-Pin LQFP Package Outline Drawing .................................................................................................... 30 Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram .......................................................................... 31 Figure 17. 204-Ball TFBGA Package ............................................................................................................................38 Figure 18. 256-Ball PBGA Package .............................................................................................................................. 46
List of Tables
Table 1. Power Management Pin Assignments ..............................................................................................................6 Table 2. Static Memory Interface Pin Assignments ........................................................................................................6 Table 3. SDRAM Interface Pin Assignments ..................................................................................................................7 Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7 Table 5. DAI Interface Pin Assignments .........................................................................................................................7 Table 6. CODEC Interface Pin Assignments ..................................................................................................................8 Table 7. SSI2 Interface Pin Assignments .......................................................................................................................8 Table 8. Serial Interface Pin Assignments ......................................................................................................................8 Table 9. LCD Interface Pin Assignments ........................................................................................................................8 Table 10. Keypad Interface Pin Assignments .................................................................................................................9 Table 11. Interrupt Controller Pin Assignments ..............................................................................................................9 Table 12. Real-Time Clock Pin Assignments ..................................................................................................................9 Table 13. PLL and Clocking Pin Assignments ................................................................................................................9 Table 14. DC-to-DC Converter Interface Pin Assignments ...........................................................................................10 Table 15. General Purpose Input/Output Pin Assignments .......................................................................................... 10 Table 16. Hardware Debug Interface Pin Assignments ................................................................................................ 10 Table 17. LED Flasher Pin Assignments ...................................................................................................................... 10 Table 18. DAI/SSI2/CODEC Pin Multiplexing ............................................................................................................... 11 Table 19. Pin Multiplexing .............................................................................................................................................11 Table 20. 208-Pin LQFP Numeric Pin Listing ............................................................................................................... 32 Table 21. 204-Ball TFBGA Ball Listing ......................................................................................................................... 40 Table 22. 256-Ball PBGA Ball Listing ........................................................................................................................... 49 Table 23. JTAG Boundary Scan Signal Ordering .........................................................................................................54 Table 24. Acronyms and Abbreviations ........................................................................................................................ 60 Table 25. Unit of Measurement ..................................................................................................................................... 60 Table 26. Pin Description Conventions ......................................................................................................................... 61
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EP7312 High-Performance, Low-Power System on Chip
Description of the EP7312's Components, Functionality, and Interfaces
The following sections describe the EP7312 in more detail. becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today's Internet appliances.
Processor Core - ARM720T
The EP7312 incorporates an ARM 32-bit RISC micro controller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include: * ARM (32-bit) and Thumb (16-bit compressed) instruction sets * Enhanced MMU for Microsoft Windows CE and other operating systems * 8 KB of 4-way set-associative cache. * Translation Look Aside Buffers with 64 Translated Entries
Memory Interfaces
There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burstmode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industryleading code density. shows the Static Memory Interface pin assignments.
Table 2. Static Memory Interface Pin Assignments
Power Management
The EP7312 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V. The device has three basic power states: * Operating -- This state is the full performance state. All the clocks and peripheral logic are enabled. * Idle -- This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press. * Standby -- This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor. Table 1 shows the power management pin assignments.
Table 1. Power Management Pin Assignments
Pin Mnemonic
nCS[5:0] A[27:0] D[31:0] nMOE/nSDCAS nMWE/nSDWE HALFWORD WORD WRITE/nSDRAS (Note) (Note) (Note)
I/O
O O I/O O O O O O
Pin Description
Chip select out Address output Data I/O ROM expansion OP enable ROM expansion write enable Halfword access select output Word access select output Transfer direction
Pin Mnemonic
BATOK nEXTPWR nPWRFL nBATCHG
I/O
I I I I
Pin Description
Battery ok input External power supply sense input Power fail sense input Battery changed sense input
MaverickKeyTM Unique ID
MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly
Note:
Pins are multiplexed. See Table 19 on page 11 for more information.
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DS508PP5
EP7312 High-Performance, Low-Power System on Chip
The second is the programmable 16- or 32-bit-wide SDRAM interface that allows direct connection of up to two banks of SDRAM, totaling 512 Mb. To assure the lowest possible power consumption, the EP7312 supports self-refresh SDRAMs, which are placed in a low-power state by the device when it enters the lowpower Standby State. Table 3 shows the SDRAM Interface pin assignments.
Table 3. SDRAM Interface Pin Assignments
to drive an infrared communication interface directly. Table 4 shows the UART pin assignments.
Table 4. Universal Asynchronous Receiver/Transmitters Pin Assignments
Pin Mnemonic
TXD[1] RXD[1] CTS
I/O
O I I I I O I O I
Pin Description
UART 1 transmit UART 1 receive UART 1 clear to send UART 1 data carrier detect UART 1 data set ready UART 2 transmit UART 2 receive Infrared LED drive output Photo diode input
Pin Mnemonic
SDCLK SDCKE nSDCS[1:0] WRITE/nSDRAS nMOE/nSDCAS nMWE/nSDWE A[27:15]/DRA[0:12] A[14:13]/DRA[12:14] PD[7:6]/SDQM[1:0] SDQM[3:2] D[31:0] (Note 2) (Note 2) (Note 2) (Note 2) (Note 1)
I/O
O O O O O O O O I/O O I/O
Pin Description
SDRAM clock output SDRAM clock enable output SDRAM chip select out SDRAM RAS signal output SDRAM CAS control signal SDRAM write enable control signal SDRAM address SDRAM internal bank select SDRAM byte lane mask SDRAM byte lane mask Data I/O
DCD DSR TXD[2] RXD[2] LEDDRV PHDIN
Digital Audio Interface (DAI)
The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI can directly interface with the Crystal CS43L41/42/43 low-power audio DACs and the Crystal CS53L32 low-power ADC. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Table 5 shows the DAI Interface pin assignments.
Table 5. DAI Interface Pin Assignments
Note:
1. Pins A[27:13] map to DRA[0:14] respectively. (i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to balance the load for large memory systems. 2. Pins are multiplexed. See Table 19 on page 11 for more information.
Pin Mnemonic
I/O
O O I O I O
Pin Description
Serial bit clock Serial data out Serial data in Sample clock Master clock input Master clock output
Digital Audio Capability
The EP7312 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7312
SCLK SDOUT SDIN LRCK MCLKIN MCLKOUT
Universal Asynchronous Receiver/Transmitters (UARTs)
The EP7312 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. The UARTs support bit rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder can be optionally switched into the RX/TX signals to/from UART 1 to enable these signals
Note:
See Table 18 on page 11 for information on pin multiplexes.
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EP7312 High-Performance, Low-Power System on Chip
CODEC Interface
The EP7312 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice communications systems. The CODEC interface is multiplexed to the same pins as the DAI and SSI2. Table 6 shows the CODEC Interface Pin Assignments.
Table 6. CODEC Interface Pin Assignments
Synchronous Serial Interface
The EP7312 Synchronous Serial Interface has these features: * ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbps operation) * Selectable serial clock polarity Table 8 shows the Synchronous Serial Interface pin assignments.
Table 8. Serial Interface Pin Assignments
Pin Mnemonic
PCMCLK PCMOUT PCMIN PCMSYNC
I/O
O O I O
Pin Description
Serial bit clock Serial data out Serial data in Frame sync
Pin Mnemonic
ADCLK ADCIN ADCOUT
I/O
O I O O O
Pin Description
SSI1 ADC serial clock SSI1 ADC serial input SSI1 ADC serial output SSI1 ADC chip select SSI1 ADC sample clock
Note:
See Table 18 on page 11 for information on pin multiplexes.
nADCCS SMPCLK
SSI2 Interface
An additional SPI/Microwire1-compatible interface is available for both master and slave mode communications. The SSI2 unit shares the same pins as the DAI and CODEC interfaces through a multiplexer. The SSI2 Interface has these features: Synchronous clock speeds of up to 512 kHz Separate 16 entry TX and RX half-word wide FIFOs Half empty/full interrupts for FIFOs Separate RX and TX frame sync signals for asymmetric traffic Table 7 shows the SSI2 Interface pin assignments.
Table 7. SSI2 Interface Pin Assignments
LCD Controller
A DMA address generator is provided that fetches video display data for the LCD controller from memory. The display frame buffer start address is programmable, allowing the LCD frame buffer to be in SDRAM, internal SRAM or external SRAM. The LCD controller has these features: * Interfaces directly to a single-scan panel monochrome STN LCD * Interfaces to a single-scan panel color STN LCD with minimal external glue logic * Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments * Video frame buffer size programmable up to 128 KB * Bits per pixel of 1, 2, or 4 bits Table 9 shows the LCD Interface pin assignments.
Table 9. LCD Interface Pin Assignments
* * * *
Pin Mnemonic
SSICLK SSITXDA SSIRXDA SSITXFR SSIRXFR
I/O
I/O O I I/O I/O
Pin Description
Serial bit clock Serial data out Serial data in Transmit frame sync Receive frame sync
Pin Mnemonic
CL1 CL2 DD[3:0] FRM M
I/O
O O O O O
Pin Description
LCD line clock LCD pixel clock out LCD serial display data bus LCD frame synchronization pulse LCD AC bias drive
Note:
See Table 18 on page 11 for information on pin multiplexes.
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DS508PP5
EP7312 High-Performance, Low-Power System on Chip
64-Key Keypad Interface
Matrix keyboards and keypads can be easily read by the EP7312. A dedicated 8-bit column driver output generates strobes for each keyboard column signal. The pins of Port A, when configured as inputs, can be selectively OR'ed together to provide a keyboard interrupt that is capable of waking the system from a STANDBY or IDLE state. The Keypad Interface has these features: * Column outputs can be individually set high with the remaining bits left at high-impedance * Column outputs can be driven all-low, all-high, or allhigh-impedance * Keyboard interrupt driven by OR'ing together all Port A bits * Keyboard interrupt can be used to wake up the system * 8x8 keyboard matrix usable with no external logic, extra keys can be added with minimal glue logic Table 10 shows the Keypad Interface Pin Assignments.
Table 10. Keypad Interface Pin Assignments
.
Table 11. Interrupt Controller Pin Assignments
Pin Mnemonic
nEINT[2:1] EINT[3] nEXTFIQ nMEDCHG/nBROM (Note)
I/O
I I I I
Pin Description
External interrupt External interrupt External Fast Interrupt input Media change interrupt input
Note:
Pins are multiplexed. See Table 19 on page 11 for more information.
Real-Time Clock
The EP7312 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt. * Driven by an external 32.768 kHz crystal oscillator Table 12 shows the Real-Time Clock pin assignments.
Table 12. Real-Time Clock Pin Assignments
Pin Mnemonic
COL[7:0]
I/O
O
Pin Description Pin Mnemonic
Keyboard scanner column drive RTCIN Real-Time Clock Oscillator Input Real-Time Clock Oscillator Output Real-Time Clock Oscillator Power Real-Time Clock Oscillator Ground RTCOUT VDDRTC VSSRTC
Pin Description
Interrupt Controller
When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled. The EP7312 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources. The Interrupt controller has these features: * Supports 22 interrupts from a variety of sources (such as UARTs, SSI1, and key matrix.) * Routes interrupt sources to the ARM720T's IRQ or FIQ (Fast IRQ) inputs * Five dedicated off-chip interrupt lines operate as level sensitive interrupts Table 11 shows the interrupt controller pin assignments.
PLL and Clocking
The EP7312 processor and peripheral clocks have these features: * Processor and peripheral clocks operate from a single 3.6864 MHz crystal or external 13 MHz clock * Programmable clock speeds allow the peripheral bus to run at 18 MHz when the processor is set to 18 MHz and at 36 MHz when the processor is set to 36, 49 or 74 MHz, and at 45 MHz when the processor is set to 90 MHz. Table 13 shows the PLL and clocking pin assignments.
Table 13. PLL and Clocking Pin Assignments
Pin Mnemonic
MOSCIN MOSCOUT VDDOSC VSSOSC
Pin Description
Main Oscillator Input Main Oscillator Output Main Oscillator Power Main Oscillator Ground
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EP7312 High-Performance, Low-Power System on Chip
DC-to-DC Converter Interface (PWM)
* Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative DC to DC converter Table 14 shows the DC-to-DC Converter Interface pin assignments.
Table 14. DC-to-DC Converter Interface Pin Assignments
Table 16. Hardware Debug Interface Pin Assignments
Pin Mnemonic
TCLK TDI TDO nTRST TMS
I/O
I I O I I
Pin Description
JTAG clock JTAG data input JTAG data output JTAG async reset input JTAG mode select
Pin Mnemonic
DRIVE[1:0] FB[1:0]
I/O
I/O I
Pin Description
PWM drive output PWM feedback input
LED Flasher
A dedicated LED flasher module can be used to generate a low frequency signal on Port D pin 0 for the purpose of blinking an LED without CPU intervention. The LED flasher feature is ideal as a visual annunciator in battery powered applications, such as a voice mail indicator on a portable phone or an appointment reminder on a PDA. Table 17 shows the LED Flasher pin assignments. * * * * Software adjustable flash period and duty cycle Operates from 32 kHz RTC clock Will continue to flash in IDLE and STANDBY states 4 mA drive current
Table 17. LED Flasher Pin Assignments
Timers
* Internal (RTC) timer * Two internal 16-bit programmable hardware countdown timers
General Purpose Input/Output (GPIO)
* Three 8-bit and one 3-bit GPIO ports * Supports scanning keyboard matrix Table 15 shows the GPIO pin assignments.
Table 15. General Purpose Input/Output Pin Assignments
Pin Mnemonic
PD[0]/LEDFLSH (Note)
I/O
O
Pin Description
LED flasher driver
Pin Mnemonic
PA[7:0] PB[7:0] PD[0]/LEDFLSH PD[5:1] PD[7:6]/SDQM[1:0] (Note) (Note)
I/O
I/O I/O I/O I/O I/O I/O I/O
Pin Description
GPIO port A GPIO port B GPIO port D GPIO port D GPIO port D GPIO port E GPIO port E
Note:
Pins are multiplexed. See Table 19 on page 11 for more information.
Internal Boot ROM
The internal 128-byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH.
PE[1:0]/BOOTSEL[1:0] (Note) PE[2]/CLKSEL (Note)
Packaging
The EP7312 is available in a 208-pin LQFP package, 256ball PBGA package, or a 204-ball TFBGA package.
Note:
Pins are multiplexed. See Table 19 on page 11 for more information.
Hardware Debug Interface
* Full JTAG boundary scan and Embedded ICE support Table 16 shows the Hardware Debug Interface pin assignments.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
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EP7312 High-Performance, Low-Power System on Chip
Pin Multiplexing
Table 18 shows the pin multiplexing of the DAI, SSI2 and the CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the DAI is controlled by the DAISEL bit in SYSCON3 (see the EP7312 User's Manual for more information).
Table 18. DAI/SSI2/CODEC Pin Multiplexing
Table 19 shows the pins that have been multiplexed in the EP7312.
Table 19. Pin Multiplexing
Signal
nMOE nMWE WRITE
Block
Static Memory Static Memory Static Memory Static Memory Static Memory GPIO System Configuration Interrupt Controller GPIO GPIO GPIO
Signal
nSDCAS nSDWE nSDRAS DRA[0:12] DRA[13:14] SDQM[1:0] CLKEN nBROM LEDFLSH BOOTSEL[1:0] CLKSEL
Block
SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM System Configuration Boot ROM select LED Flasher System Configuration System Configuration
Pin Mnemonic
SSICLK SSITXDA SSIRXDA SSITXFR SSIRXFR BUZ
I/O
I/O O I I/O I O
DAI
SCLK SDOUT SDIN LRCK MCLKIN MCLKOUT
SSI2
SSICLK SSITXDA SSIRXDA SSITXFR SSIRXFR
CODEC
PCMCLK PCMOUT PCMIN PCMSYNC p/u
A[27:15] A[14:13] PD[7:6] RUN nMEDCHG PD[0] PE[1:0] PE[2]
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EP7312 High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated EP7312 completes a low-power system solution. All necessary interface logic is integrated on-chip.
CRYSTAL CRYSTAL
MOSCIN RTCIN
DD[0-3] CL1 CL2 FRM M COL[0-7]
LCD
D[0-31] A[0-27] nMOE WRITE
KEYBOARD
PA[0-7] PB[0-7] PD[0-7] PE[0-2]
SDCAS
x16 SDRAM x16 SDRAM
x16 SDRAM x16 SDRAM
SDCS[0] SDQM[0-3] SDCS[1] SDQM[0-3]
EP7312
SDRAS/
nPOR nPWRFL BATOK nEXTPWR nBATCHG RUN WAKEUP DRIVE[0-1] FB[0-1]
POWER SUPPLY UNIT AND COMPARATORS
DC INPUT
BATTERY
DC-TO-DC CONVERTERS
nCS[0] nCS[1]
x16 FLASH x16 FLASH
x16 FLASH x16 FLASH
CS[n] WORD
SSICLK SSITXFR SSITXDA SSIRXDA SSIRXFR LEDDRV PHDIN RXD[[1/2] TXD[1/2] DSR CTS DCD ADCCLK nADCCS ADCOUT ADCIN SMPCLK
CODEC/SSI2/ DAI
IR LED AND PHOTODIODE
EXTERNAL MEMORYMAPPED EXPANSION
BUFFERS
2x RS-232 TRANSCEIVERS
nCS[2] nCS[3]
ADDITIONAL I/O
BUFFERS AND LATCHES
ADC
DIGITIZER
LEDFLSH
Figure 1. A Fully-Configured EP7312-Based System Note: A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Pad Input Current Storage Temperature, No Power 2.9 V 3.6 V 10 mA/pin; 100 mA cumulative -40C to +125C
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage DC I/O Supply Voltage (Pad Ring) DC Input / Output Voltage Operating Temperature 2.5 V 0.2 V 2.3 V - 3.5 V O-I/O supply voltage Extended -20C to +70C; Commercial 0C to +70C; Industrial -40C to +85C
DC Characteristics
All characteristics are specified at V DDCORE = 2.5 V, VDDIO = 3.3 V and VSS = 0 V over an operating temperature of 0C to +70C for all frequencies of operation. The current consumption figures have test conditions specified per parameter."
Symbol
VIH VIL VT+
Parameter
CMOS input high voltage CMOS input low voltage Schmitt trigger positive going threshold Schmitt trigger negative going threshold Schmitt trigger hysteresis CMOS output high voltagea
Min
0.65 x VDDIO VSS - 0.3 -
Typ
-
Max
VDDIO + 0.3 0.25 x VDDIO 2.1
Unit
V V V
Conditions
VDDIO = 2.5 V VDDIO = 2.5 V
VTVhst
0.8 0.1 VDD - 0.2 2.5 2.5 25 8
-
0.4 0.3 0.5 0.5 1.0 100 10.0
V V V V V V V V A A pF VIL to VIH IOH = 0.1 mA IOH = 4 mA IOH = 12 mA IOL = -0.1 mA IOL = -4 mA IOL = -12 mA VIN = VDD or GND VOUT = VDD or GND
VOH
Output drive 1a Output drive 2a CMOS output low voltagea
VOL
Output drive 1a Output drive 2a
IIN IOZ CIN
Input leakage current Bidirectional 3-state leakage currentb c Input capacitance
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
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EP7312 High-Performance, Low-Power System on Chip
Symbol
COUT CI/O
Parameter
Output capacitance Transceiver capacitance
Min
8 8
Typ
-
Max
10.0 10.0
Unit
pF pF
Conditions
IDDSTANDBY
@ 25 C
Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V
-
77 41
-
A
Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD 0.1 V, VIL = GND 0.1 V Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD 0.1 V, VIL = GND 0.1 V Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD 0.1 V, VIL = GND 0.1 V Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = V DD 0.1 V, VIL = GND 0.1 V Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = V DD 0.1 V, VIL = GND 0.1 V Minimum standby voltage for state retention, internal SRAM cache, and RTC operation only
IDDSTANDBY
@ 70 C
Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V
-
-
570 111
A
IDDSTANDBY
@ 85 C
Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V 1693 163 A
IDD idle at 74 MHz
Idle current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V
-
6 10
-
mA
IDD IDLE at 90 MHz
Idle current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V
-
7 11
-
mA
VDD STANDBY Standby supply voltage
2.0
-
-
V
a. b. c. Note:
Refer to the strength column in the pin assignment tables for all package types. Assumes buffer has no pull-up or pull-down resistors. The leakage value given assumes that the pin is configured as an input pin but is not currently being driven. 1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V 2) A typical design will provide 3.3 V to the I/O supply (i.e., VDDIO), and 2.5 V to the remaining logic. This is to allow the I/O to be compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs). 2) Pull-up current = 50 A typical at VDD = 3.3 V.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Timings
Timing Diagram Conventions
This data sheet contains timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.
C lo c k
H ig h
to
Low
H ig h /L o w
to
H ig h
Bus
C hange
Bus
V a lid
U n d e fin e d /In v a lid
V a lid
Bus
to
T r is ta te
B u s / S ig n a l O m is s io n
Figure 2. Legend for Timing Diagrams
Timing Conditions
Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at VDDIO = 3.1 - 3.5 V and V SS = 0 V over an operating temperature of -40C to +85C. Pin loadings is 50 pF. The timing values are referenced to 1/2 V DD.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
15
EP7312 High-Performance, Low-Power System on Chip
SDRAM Interface
Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes.
Parameter
SDCLK rising edge to SDCS assert delay time SDCLK rising edge to SDCS deassert delay time SDCLK rising edge to SDRAS assert delay time SDCLK rising edge to SDRAS deassert delay time SDCLK rising edge to SDRAS invalid delay time SDCLK rising edge to SDCAS assert delay time SDCLK rising edge to SDCAS deassert delay time SDCLK rising edge to ADDR transition time SDCLK rising edge to ADDR invalid delay time SDCLK rising edge to SDMWE assert delay time SDCLK rising edge to SDMWE deassert delay time DATA transition to SDCLK rising edge time SDCLK rising edge to DATA transition hold time SDCLK rising edge to DATA transition delay time
Symbol
tCSa tCSd tRAa tRAd tRAnv tCAa tCAd tADv tADx tMWa tMWd tDAs tDAh tDAd
Min
0 -3 1 -3 2 -2 -5 -3 -2 -2 -4 0
Typ
2 2 3 1 4 2 0 1 2 1 0 -
Max
4 10 7 10 7 5 3 5 5 5 4 2 1 15
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
SDRAM Load Mode Register Cycle
SDCLK tCSa SDCS tRAa SDRAS tRAd tCSd
tCAa SDCAS
tCAd
tADv ADDR
tADx
DATA
SDQM tMWa SDMWE tMWd
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
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EP7312 High-Performance, Low-Power System on Chip
SDRAM Burst Read Cycle
SDCLK
tCSa SDCS tCSd tRAa SDRAS tRAd
tCSa tCSd tRAnv
tCAa SDCAS tADv ADDR tCAd tADv
ADRAS
ADCAS
tDAs tDAs tDAs tDAs
DATA
D1
tDAh
D2
tDAh
D3
tDAh
D4
tDAh
SDQM [0:3]
SDMWE
Figure 4. SDRAM Burst Read Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
SDRAM Burst Write Cycle
SDCLK
tCSa SDCS tRAa SDRAS tRAd tCSd
tCSa tCSd
tCAa SDCAS tADv ADDR tDAd DATA tADv tCAd
ADRAS
tDAd tDAd
ADCAS
tDAd
D1
D2
D3
D4
SDQM
0
tMWa tMWd
SDMWE
Figure 5. SDRAM Burst Write Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
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EP7312 High-Performance, Low-Power System on Chip
SDRAM Refresh Cycle
SDCLK tCSa SDCS tRAa SDRAS tCAd SDCAS tCAa tRAd tCSd
SDATA
ADDR
SDQM [3:0]
SDMWE
Figure 6. SDRAM Refresh Cycle Timing Measurement
Note:
1. Timings are shown with CAS latency = 2 2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading. Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Static Memory
Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes.
Parameter
EXPCLK rising edge to nCS assert delay time EXPCLK falling edge to nCS deassert hold time EXPCLK rising edge to A assert delay time EXPCLK falling edge to A deassert hold time EXPCLK rising edge to nMWE assert delay time EXPCLK rising edge to nMWE deassert hold time EXPCLK falling edge to nMOE assert delay time EXPCLK falling edge to nMOE deassert hold time EXPCLK falling edge to HALFWORD deassert delay time EXPCLK falling edge to WORD assert delay time EXPCLK rising edge to data valid delay time EXPCLK falling edge to data invalid delay time Data setup to EXPCLK falling edge time EXPCLK falling edge to data hold time EXPCLK rising edge to WRITE assert delay time EXPREADY setup to EXPCLK falling edge time EXPCLK falling edge to EXPREADY hold time
Symbol
tCSd tCSh tAd tAh tMWd tMWh tMOEd tMOEh tHWd tWDd tDv tDnv tDs tDh tWRd tEXs tEXh
Min
2 2 4 3 3 3 3 2 2 2 8 6 5 -
Typ
8 7 9 10 6 6 7 7 8 8 13 15 11 -
Max
20 20 16 19 10 10 10 10 20 16 21 30 1 3 23 0 0
Unit
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
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EP7312 High-Performance, Low-Power System on Chip
Static Memory Single Read Cycle
EXPCLK tCSd nCS tAd A tCSh
nMWE tMOEd nMOE tHWd HALFWORD tWDd WORD tDs D tEXs EXPRDY tWRd WRITE tEXh tDh tMOEh
Figure 7. Static Memory Single Read Cycle Timing Measurement
Note:
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2. Address, Halfword, Word, and Write hold state until next cycle.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Static Memory Single Write Cycle
EXPCLK tCSd nCS tAd A tMWd nMWE tMWh tCSh
nMOE tHWd HALFWORD
tWDd WORD tDv D tEXs EXPRDY tEXh
WRITE
Figure 8. Static Memory Single Write Cycle Timing Measurement
Note:
1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 2. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions. 3. Address, Data, Halfword, Word, and Write hold state until next cycle.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
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EP7312 High-Performance, Low-Power System on Chip
Static Memory Burst Read Cycle
EXPCLK tCSd nCS tAd A tAh tAh tAh tCSh
nMWE tMOEd nMOE tHWd HALF WORD tMOEh
WORD
tWDd tDs tDh tDs tDh tDs tDh tDs tDh
D tEXs EXPRDY tWRd WRITE tEXh
Figure 9. Static Memory Burst Read Cycle Timing Measurement
Note: 1. Four cycles are shown in the above diagram (minimum wait states, 1-0-0-0). This is the maximum number of consecutive cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively. 2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 3. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to determine the number of wait states, and no idle cycles are inserted between successive non-sequential ROM/expansion cycles. This improves performance so the SQAEN bit should always be set where possible. 4. Address, Halfword, Word, and Write hold state until next cycle.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Static Memory Burst Write Cycle
EXPCLK tCSd nCS tAd A tMWd nMWE tMWh tMWd tMWh tMWd tMWh tMWd tMWh tAh tAh tAh tCSh
nMOE tHWd HALF WORD
WORD
tWDd tDv tDnv tDv tDnv tDv tDnv tDv
D tEXs EXPRDY tEXh
WRITE
Figure 10. Static Memory Burst Write Cycle Timing Measurement
Note:
1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively. 2. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at 18.432 MHz, and 77 ns at 13 MHz), by either driving EXPRDY low and/or by programming a number of wait states. EXPRDY is sampled on the falling edge of EXPCLK before the data transfer. If low at this point, the transfer is delayed by one clock period where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity. 3. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with valid timing under zero wait state conditions. 4. Address, Data, Halfword, Word, and Write hold state until next cycle.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
25
EP7312 High-Performance, Low-Power System on Chip
SSI1 Interface
Parameter
ADCCLK falling edge to nADCCSS deassert delay time ADCIN data setup to ADCCLK rising edge time ADCIN data hold from ADCCLK rising edge time ADCCLK falling edge to data valid delay time ADCCLK falling edge to data invalid delay time
Symbol
tCd tINs tINh tOvd tOd
Min
9 -7 -2
Max
10 15 14 13 3
Unit
ms ns ns ns ns
ADC CLK
tCd
nADC CSS
tINs tINh
ADCIN
tOvd tOd
ADC OUT
Figure 11. SSI1 Interface Timing Measurement
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
SSI2 Interface
Parameter
SSICLK period (slave mode) SSICLK high time SSICLK low time SSICLK rise/fall time SSICLK rising edge to RX and/or TX frame sync high time SSICLK rising edge to RX and/or TX frame sync low time SSIRXFR and/or SSITXFR period SSIRXDA setup to SSICLK falling edge time SSIRXDA hold from SSICLK falling edge time SSICLK rising edge to SSITXDA data valid delay time SSITXDA valid time
Symbol
tclk_per tclk_high tclk_low tclkrf tFRd tFRa tFR_per tRXs tRXh tTXd tTXv
Min
185 925 925 3 960 3 3 960
Max
2050 1025 1025 18 3 8 990 7 7 2 990
Unit
ns ns ns ns ns ns ns ns ns ns ns
tclk_per
tclk_high
tclk_low
SSI CLK
tclkrf tFRd tFRa tFR_per
SSIRXFR/ SSITXFR
tRXh tRXs
SSI RXDA
tTXd
D7
D2
D1
D0
SSI TXDA
D7
tTXv
D2
D1
D0
Figure 12. SSI2 Interface Timing Measurement
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
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EP7312 High-Performance, Low-Power System on Chip
LCD Interface
Parameter
CL[2] falling to CL[1] rising delay time CL[1] falling to CL[2] rising delay time CL[1] falling to FRM transition time CL[1] falling to M transition time CL[2] rising to DD (display data) transition time
Symbol
tCL1d tCL2d tFRMd tMd tDDd
Min
- 10
Max
25 3,475 10,425 20 20
Unit
ns ns ns ns ns
80 300
- 10 - 10
CL[2] tCL1d CL[1] tFRMd FRM tMd M tDDd DD [3:0] tCL2d
Figure 13. LCD Controller Timing Measurement
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
JTAG Interface
Parameter
TCK clock period TCK clock high time TCK clock low time JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance
Symbol
tclk_per tclk_high tclk_low tJPs tJPh tJPco tJPzx tJPxz
Min
2 1 1 -
Max
0 3 10 12 19
Units
ns ns ns ns ns ns ns ns
tclk_per tclk_high TCK tJPs TMS tJPh tclk_low
TDI tJPzx TDO tJPco tJPxz
Figure 14. JTAG Timing Measurement
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
29
EP7312 High-Performance, Low-Power System on Chip
Packages
208-Pin LQFP Package Characteristics
29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011)
27.80 (1.094) 28.20 (1.110)
29.60 (1.165) 30.40 (1.197)
EP7312
208-Pin LQFP
0.50 (0.0197) BSC
Pin 1 Indicator
Pin 208 Pin 1
0.45 (0.018) 0.75 (0.030)
1.35 (0.053) 1.45 (0.057)
1.00 (0.039) BSC
0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 1.60 (0.063) 0.05 (0.002) 0.15 (0.006)
0 MIN 7 MAX
Figure 15. 208-Pin LQFP Package Outline Drawing
Note: 1) 2) 3) 4) Dimensions are in millimeters (inches), and controlling dimension is millimeter. Drawing above does not reflect exact package pin count. Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. For pin locations, please see Figure 16. For pin descriptions see the EP7312 User's Manual.
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
208-Pin LQFP Pin Diagram
nURESET nMEDCHG/nBROM nPOR BATOK nEXTPWR nBATCHG D[7] VSSIO A[7] D[8] A[8] D[9] A[9] D[10] A[10] D[11] VSSIO VDDIO A[11] D[12] A[12] D[13] A[13]\DRA[14] D[14] A[14]/DRA[13] D[15] A[15]/DRA[12] D[16] A[16]/DRA[11] D[17] A[17]/DRA[10] nTRST VSSIO VDDIO D[18] A[18/DRA[9] D[19] A[19]/DRA[8] D[20] A[20]/DRA[7] VSSIO D[21] A[21]/DRA[6] D[22] A[22]/DRA[5] D[23] A[23]/DRA[4] D[24] VSSIO VDDIO A[24]/DRA[3] HALFWORD 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
Note:
1. N/C should not be grounded but left as no connects.
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DS508PP5
nCS[5] VDDIO VSSIO EXPCLK WORD WRITE/nSDRAS RUN/CLKEN EXPRDY TXD[2] RXD[2] TDI VSSIO PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] VDDIO TDO PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD[1] VSSIO PHDIN CTS RXD[1] DCD DSR nTEST[1] nTEST[0] EINT[3] nEINT[2] nEINT[1] nEXTFIQ PE[2]/CLKSEL PE[1]BOOTSEL[1] PE[0]BOOTSEL[0] VSSRTC RTCOUT RTCIN VDDRTC N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
VDDOSC MOSCIN MOSCOUT VSSOSC WAKEUP nPWRFL A[6] D[6] A[5] D[5] VDDIO VSSIO A[4] D[4] A[3] D[3] A[2] VSSIO D[2] A[1] D[1] A[0] D[0] VSSCORE VDDCORE VSSIO VDDIO CL[2] CL[1] FRM M DD[3] DD[2] VSSIO DD[1] DD[0] nSDCS[1] nSDCS[0] SDQM[3] SDQM[2] VDDIO VSSIO SDCKE SDCLK nMWE/nSDWE nMOE/nSDCAS VSSIO nCS[0] nCS[1] nCS[2] nCS[3] nCS[4]
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
EP7312
208-Pin LQFP
(Top View)
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
D[25] A[25]/DRA[2] D[26] A[26]/DRA[1] D[27] A[27]/DRA[0] VSSIO D[28] D[29] D[30] D[31] BUZ COL[0] COL[1] TCLK VDDIO COL[2] COL[3] COL[4] COL[5] COL[6] COL[7] FB[0] VSSIO FB[1] SMPCLK ADCOUT ADCCLK DRIVE[0] DRIVE[1] VDDIO VSSIO VDDCORE VSSCORE nADCCS ADCIN SSIRXFR SSIRXDA SSITXDA SSITXFR VSSIO SSICLK PD[0]/LEDFLSH PD[1] PD[2] PD[3] TMS VDDIO PD[4] PD[5] PD[6]/SDQM[0] PD[7]/SDQM[1]
Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
31
EP7312 High-Performance, Low-Power System on Chip
208-Pin LQFP Numeric Pin Listing
Table 20. 208-Pin LQFP Numeric Pin Listing
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Signal nCS[5] VDDIO VSSIO EXPCLK WORD WRITE/nSDRAS RUN/CLKEN EXPRDY TXD[2] RXD[2] TDI VSSIO PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] VDDIO TDO PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD[1] VSSIO PHDIN CTS RXD[1] DCD 1 1 1 1 1 1 1 1 1 1 1 1 Input Input Input Input Input Input Input Input Input 1 1 1 1 1 1 1 1 Input Input Input Input Input Input Input Input with p/u* 1 1 1 1 1 1 High Low Low Low Strength 1
Reset State Low
Type O Pad Pwr Pad Gnd I O O O I O I I Pad Gnd
Description Chip select 5 Digital I/O power, 3.3 V I/O ground Expansion clock input Word access select output Transfer direction / SDRAM RAS signal output Run output / clock enable output Expansion port ready input UART 2 transmit data output UART 2 receive data input JTAG data input I/O ground GPIO port B GPIO port B GPIO port B GPIO port B GPIO port B GPIO port B GPIO port B GPIO port B Digital I/O power, 3.3 V JTAG data out GPIO port A GPIO port A GPIO port A GPIO port A GPIO port A GPIO port A GPIO port A GPIO port A IR LED drive UART 1 transmit data out I/O ground Photodiode input UART 1 clear to send input UART 1 receive data input UART 1 data carrier detect

I/O I/O I/O I/O I/O I/O I/O I/O Pad Pwr

O I/O I/O I/O I/O I/O I/O I/O I/O O O Pad Gnd I I I I
Low High High
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32
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 Signal DSR nTEST[1] nTEST[0] EINT[3] nEINT[2] nEINT[1] nEXTFIQ PE[2]/CLKSEL PE[1]/BOOTSEL[1] PE[0]/BOOTSEL[0] VSSRTC RTCOUT RTCIN VDDRTC N/C PD[7]/SDQM[1] PD[6]/SDQM[0] PD[5] PD[4] VDDIO TMS PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSICLK VSSIO SSITXFR SSITXDA SSIRXDA SSIRXFR ADCIN nADCCS VSSCORE VDDCORE VSSIO VDDIO DRIVE[1] DRIVE[0] ADCCLK ADCOUT 2 2 1 1 High / Low High / Low Low Low 1 High 1 1 Low Low with p/u* 1 1 1 1 1 Low Low Low Low 1 1 1 1 Low Low Low Low I/O I/O I/O I/O Pad Pwr I I/O I/O I/O I/O I/O Pad Gnd I/O O I GPIO port D / SDRAM byte lane mask GPIO port D / SDRAM byte lane mask GPIO port D GPIO port D Digital I/O power, 3.3 V JTAG mode select GPIO port D GPIO port D GPIO port D GPIO port D / LED blinker output DAI/CODEC/SSI2 serial clock I/O ground DAI/CODEC/SSI2 serial clock DAI/CODEC/SSI2 serial data output DAI/CODEC/SSI2 serial data input DAI/CODEC/SSI2 frame sync SSI1 ADC serial input SSI1 ADC chip select Core ground Core power, 2.5 V I/O ground Digital I/O power, 3.3 V PWM drive output PWM drive output SSI1 ADC serial clock SSI1 ADC serial data output 1 1 1 Input Input Input With p/u* With p/u* Strength
Reset State
Type I I I I I I I
Description UART 1 data set ready input Test mode select input Test mode select input External interrupt External interrupt input External interrupt input External fast interrupt input GPIO port E / clock input mode select GPIO port E / boot mode select GPIO port E / Boot mode select Real time clock ground Real time clock oscillator output Real time clock oscillator input Real time clock power, 2.5 V

I/O I/O I/O RTC Gnd O I RTC power
Input
Input
I/O I O Core ground Core Pwr Pad Gnd Pad Pwr I/O I/O O O
(c)
DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
33
EP7312 High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin No. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 Signal SMPCLK FB[1] VSSIO FB[0] COL[7] COL[6] COL[5] COL[4] COL[3] COL[2] VDDIO TCLK COL[1] COL[0] BUZ D[31] D[30] D[29] D[28] VSSIO A[27]/DRA[0] D[27] A[26]/DRA[1] D[26] A[25]/DRA[2] D[25] HALFWORD A[24]/DRA[3] VDDIO VSSIO D[24] A[23]/DRA[4] D[23] A[22]/DRA[5] D[22] A[21]/DRA[6] D[21] VSSIO A[20]/DRA[7] 1 Low 1 1 1 1 1 1 1 2 1 2 1 2 1 1 1 Low Low Low Low Low Low Low Low -- -- Low Low Low Low Low Low Low 1 1 1 1 1 1 1 High High Low Low Low Low Low 1 1 1 1 1 1 High High High High High High Strength 1
Reset State Low
Type O I Pad Gnd I O O O O O O Pad Pwr I O O O I/O I/O I/O I/O Pad Gnd O I/O O I/O O I/O O O Pad Pwr Pad Gnd I/O O I/O O I/O O I/O Pad Gnd O
Description SSI1 ADC sample clock PWM feedback input I/O ground PWM feedback input Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Digital I/O power, 3.3 V JTAG clock Keyboard scanner column drive Keyboard scanner column drive Buzzer drive output Data I/O Data I/O Data I/O Data I/O I/O ground System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O Halfword access select output System byte address / SDRAM address Digital I/O power, 3.3 V I/O ground Data I/O System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O I/O ground System byte address / SDRAM address
(c)
34
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin No. 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Signal D[20] A[19]/DRA[8] D[19] A[18]/DRA[9] D[18] VDDIO VSSIO nTRST A[17]/DRA[10] D[17] A[16]/DRA[11] D[16] A[15]/DRA[12] D[15] A[14]/DRA[13] D[14] A[13]/DRA[14] D[13] A[12] D[12] A[11] VDDIO VSSIO D[11] A[10] D[10] A[9] D[9] A[8] D[8] A[7] VSSIO D[7] nBATCHG nEXTPWR BATOK nPOR nMEDCHG/nBROM nURESET VDDOSC MOSCIN MOSCOUT VSSOSC Schmitt Schmitt 1 Low 1 1 1 1 1 1 1 1 Low Low Low Low Low Low Low Low 1 1 1 1 1 1 1 1 1 1 1 1 1 Low Low Low Low Low Low Low Low Low Low Low Low Low Strength 1 1 1 1 1
Reset State Low Low Low Low Low
Type I/O O I/O O I/O Pad Pwr Pad Gnd I O I/O O I/O O I/O O I/O O I/O O I/O O Pad Pwr Pad Gnd I/O O I/O O I/O O I/O O Pad Gnd I/O I I I I I I Oscillator Power I O Oscillator Ground
Description Data I/O System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O Digital I/O power, 3.3 V I/O ground JTAG async reset input System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O System byte address / SDRAM address Data I/O System byte address Data I/O System byte address Digital I/O power, 3.3 V I/O ground Data I/O System byte address Data I/O System byte address Data I/O System byte address Data I/O System byte address I/O ground Data I/O Battery changed sense input External power supply sense input Battery OK input Power-on reset input Media change interrupt input / internal ROM boot enable User reset input Oscillator power in, 2.5 V Main oscillator input Main oscillator output Oscillator Ground
(c)
DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
35
EP7312 High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 Signal WAKEUP nPWRFL A[6] D[6] A[5] D[5] VDDIO VSSIO A[4] D[4] A[3] D[3] A[2] VSSIO D[2] A[1] D[1] A[0] D[0] VSSCORE VDDCORE VSSIO VDDIO CL[2] CL[1] FRM M DD[3] DD[2] VSSIO DD[1] DD[0] nSDCS[1] nSDCS[0] SDQM[3] SDQM[2] VDDIO VSSIO SDCKE SDCLK nMWE/nSDWE 2 2 1 Low Low High 1 1 1 1 2 2 Low Low High High Low Low 1 1 1 1 1 1 Low Low Low Low Low Low 1 2 1 2 1 Low Low Low Low Low 1 1 2 1 2 Low Low Low Low Low 1 1 1 1 Low Low Low Low Strength Schmitt
Reset State
Type I I O I/O Out I/O Pad Pwr Pad Gnd O I/O O I/O O Pad Gnd I/O O I/O O I/O Core ground Core Pwr Pad ground Pad Power O O O O I/O I/O Pad Gnd I/O I/O O O I/O I/O Pad Pwr Pad Gnd I/O I/O O
Description System wake up input Power fail sense input System byte address Data I/O System byte address Data I/O Digital I/O power, 3.3 V I/O ground System byte address Data I/O System byte address Data I/O System byte address I/O ground Data I/O System byte address Data I/O System byte address Data I/O Core ground Core power, 2.5 V I/O ground Digital I/O power, 3.3 V LCD pixel clock out LCD line clock LCD frame synchronization pulse LCD AC bias drive LCD serial display data LCD serial display data I/O ground LCD serial display data LCD serial display data SDRAM chip select 1 SDRAM chip select 0 SDRAM byte lane mask SDRAM byte lane mask Digital I/O power, 3.3 V I/O ground SDRAM clock enable output SDRAM clock out ROM, expansion write enable/ SDRAM write enable control signal ROM, expansion OP enable/SDRAM CAS control signal I/O ground Chip select 0 Chip select 1
202 203 204 205
nMOE/nSDCAS VSSIO nCS[0] nCS[1]
1
High
O Pad Gnd
1 1
High High
O O
(c)
36
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
Pin No. 206 207 208 Signal nCS[2] nCS[3] nCS[4] Strength 1 1 1
Reset State High High High
Type O O O
Description Chip select 2 Chip select 3 Chip select 4
*"With p/u" means with internal pull-up of 100 KOhms on the pin.
Strength 1 = 4 ma Strength 2 = 12 ma Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
(c)
DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
37
EP7312 High-Performance, Low-Power System on Chip
204-Ball TFBGA Package Characteristics
TOP VIEW A1 CORNER
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y A
O0.08 M C
BOTTOM VIEW A1 CORNER
A B C D E F G H J K L M N P R T U V W Y 0.65 12.35
O0.15 M C A B O0.25~0.35(204X)
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
130.05
12.35
0.65
B 0.530.05 0.20 C
0.15(4X) C
130.05
0.10 C
Ball Pitch : 0.65
0.36 0.20~0.30 C 1.20 MAX.
Substrate Thickness : 0.36 Mold Thickness : 0.53
SEATING PLANE
Ball Diameter : 0.3
Figure 17. 204-Ball TFBGA Package
(c)
38
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
204-Ball TFBGA Pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A
VDDIO
EXPCLK
nCS[3]
nCS[1]
nMWE/ SDQM[2 nSDCS[1] DD[2] nSDWE ] nMOE/ SDCKE nSDCS[0] DD[1] nSDCAS
FRM
CL[1]
GNDCORE D[1]
A[2]
D[4]
A[5]
nPWRFL
MOSCOUT
GNDIO
GNDIO
GNDIO
A
B
WORD RUN/ CLKEN
VDDIO
nCS[5]
nCS[2]
M
CL[2]
D[0]
A[1]
D[3]
A[4]
D[6]
WAKEUP
MOSCIN
GNDIO
GNDIO
nURESET B
C
EXPRDY
VDDIO
nCS[4]
nCS[0] SDCLK SDQM[3]
DD[0]
DD[3]
VDDCORE
A[0]
D[2]
A[3]
D[5]
A[6]
GNDOSC
VDDOSC
GNDIO
BATOK
nPOR
C
D
PB[7]
RXD[2]
VDDIO WRITE/ nSDRAS
GNDIO
nBATCHG
A[7]
D
E
PB[4]
TXD[2]
nMEDCHG/n nEXTPWR BROM
D[9]
E
F
PB[3]
PB[6]
TDI
D[7]
A[8]
D[10]
F
G
PB[1]
PB[2]
PB[5]
D[8]
A[9]
D[11]
G
H
PA[7]
TDO
PB[0]
A[10]
D[12]
A[12]
H
J
PA[4]
PA[5]
PA[6]
A[11]
D[13] A[14]/ DRA[13]
A[13]/ J DRA[14]
K
PA[1]
PA[2]
VDDIO
D[14]
D[15]
K
L TXD[1]
LEDDRV
PA[3]
VDDIO A[15]/ DRA[12]
D[16] A[17]/ DRA[10]
A[16]/ L DRA[11]
M RXD[1]
CTS
PA[0]
nTRST A[18]/ DRA[9]
M
N
DSR
nTEST[1] PHDIN
D[17]
D[19] A[20]/ DRA[7]
N
P EINT[3] nEINT[2]
DCD
D[18] A[19]/ DRA[8]
D[20] A[21]/ DRA6
P
R nEXTFIQ PE[1]/ BOOT SEL[1]
PE2/ nTEST[0] CLKSEL PE[0]/ BOOT nEINT[1] SEL[0]
D[22]
R
T
D[21]
D[23]
A[22]/ DRA5 A[23]/ DRA4 A[24]/ DRA3
T
U GNDRTC RTCOUT
RTCIN PD[7]/ SDQM[1] PD[6]/ SDQM[0] SSIRXD A A[26]/ DRA[1] A[27]/ DRA[0]
HALF WORD
D[24]
U
V VDDRTC
GNDIO
GNDIO
PD[4]
PD[2]
SSICLK
nADCCS
VDDIO
ADCCLK COL[7] COL[4] TCLK
BUZ
D[29]
VDDIO
VDDIO
V
W GNDIO
GNDIO
GNDIO
TMS
PD[1]
SSITXFR SSIRXFR GNDCORE
DRIVE[1]
ADCOUT FB[0] COL[5] COL[2] COL[0]
D[30]
D[26]
VDDIO
D[25]
W
Y
GNDIO
GNDIO
GNDIO
PD[5]
PD[3]
PD[0]/ LED SSITXDA FLSH
ADCIN
VDDCORE
DRIVE[0]
SMPCLK FB[1] COL[6] COL[3] COL[1]
D[31]
D[28]
D[27]
A[25]/ DRA[2]
VDDIO
Y
(c)
DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
39
EP7312 High-Performance, Low-Power System on Chip
204-Ball TFBGA Ball Listing
The list is ordered by ball location.
Table 21. 204-Ball TFBGA Ball Listing
Ball Location Name
Strength
Reset State
Type
Description
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13
VDDIO EXPCLK nCS[3] nCS[1] nMWE/nSDWE SDQM[2] nSDCS[1] DD[2] FRM CL[1] VSSCORE D[1] A[2] D[4] A[5] nPWRFL MOSCOUT VSSIO VSSIO VSSIO WORD VDDIO nCS[5] nCS[2] nMOE/nSDCAS SDCKE nSDCS[0] DD[1] M CL[2] D[0] A[1] D[3] 1 1 1 2 1 1 1 1 1 2 2 Low High High Low High Low Low Low Low Low Low 1 Low 1 2 1 1 Low Low Low Low 1 1 1 1 2 1 1 1 1 High High High Low High Low Low Low
Pad power I O O O O O O O O Core ground I/O O I/O O I O Pad ground Pad ground Pad ground O Pad power O O O O O O O 0 I/O O I/O
Digital I/O power, 3.3 V Expansion clock input Chip select 3 Chip select 1 ROM, expansion write enable/ SDRAM write enable control signal SDRAM byte lane mask SDRAM chip select 2 LCD serial display data LCD frame synchronization pulse LCD line clock Core ground Data I/O System byte address Data I/O System byte address Power fail sense input Main oscillator out I/O ground I/O ground I/O ground Word access select output Digital I/O power, 3.3 V Chip select 5 Chip select 2 ROM, expansion OP enable/SDRAM CAS control signal SDRAM clock enable output SDRAM chip select 0 LCD serial display data LCD AC bias drive LCD pixel clock out Data I/O System byte address Data I/O
(c)
40
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location Name
Strength 1 1 Schmitt
Reset State Low Low
Type
Description
B14 B15 B16 B17 B18 B19 B20 C1 C2
A[4] D[6] WAKEUP MOSCIN VSSIO VSSIO nURESET RUN/CLKEN EXPRDY
O I/O I I Pad ground Pad ground
System byte address Data I/O System wake up input Main oscillator input I/O ground I/O ground User reset input Run output / clock enable output Expansion port ready input Digital I/O power, 3.3 V Chip select 4 Chip select 0 SDRAM clock out SDRAM byte lane mask LCD serial display data LCD serial display data Digital core power, 2.5 V System byte address Data I/O System byte address Data I/O System byte address PLL ground Oscillator power in, 2.5V I/O ground Battery ok input
Schmitt 1 1 Low
I 0 I
C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
VDDIO nCS[4] nCS[0] SDCLK SDQM[3] DD[0] DD[3] VDDCORE A[0] D[2] A[3] D[5] A[6] VSSOSC VDDOSC VSSIO BATOK 2 1 2 1 1 Low Low Low Low Low 1 1 2 2 1 1 High High Low Low Low Low
Pad power O O O O O O Core power O I/O O I/O O Oscillator ground Oscillator power Pad ground I
(c)
DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
41
EP7312 High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location Name
Strength Schmitt 1
Reset State
Type
Description
C20 D1 D2 D3 D18 D19 D20 E1 E2 E3 E18 E19 E20 F1
nPOR PB[7] RXD[2] VDDIO VSSIO nBATCHG A[7] PB[4] TXD[2] WRITE/nSDRAS nMEDCHG/nBROM nEXTPWR D[9] PB[3]
I
Power-on reset input GPIO port B UART 2 receive data input Digital I/O power, 3.3V I/O ground Battery changed sense input System byte address GPIO port B UART 2 transmit data output Transfer direction / SDRAM RAS signal output Media change interrupt input / internal ROM boot enable External power supply sense input Data I/O GPIO port B GPIO port B
Input
I I Pad power Pad ground I
1 1 1 1
Low
O I O O I I
Input
High Low
1 1
Low
I/O I/O
Input

F2 F3 F18 F19 F20 G1
PB[6] TDI D[7] A[8] D[10] PB[1]
1 with p/u* 1 1 1 1
Input
I/O I
JTAG data input Data I/O System byte address Data I/O
Low Low Low
I/O O I/O I/O
Input

G2
PB[2]
1
Input
I/O
GPIO port B
G3
PB[5]
1
Input
I/O
GPIO port B
G18 G19 G20 H1
D[8] A[9] D[11] PA[7]
1 1 1 1
Input
I/O O I/O I/O
Data I/O System byte address Data I/O GPIO port A
Low Low
Input

H[2]
TDO
1
Input
O
JTAG data out
H[3] H[18] H19 H20 J1
PB[0] A[10] D[12] A[12] PA[4]
1 1 1 1 1
Input
I/O O I/O O I/O
GPIO port B System byte address Data I/O System byte address GPIO port A
Low Low Low
Input
(c)
42
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location Name
Strength
Reset State
Type
Description
J2
PA[5]
1
Input

I/O
GPIO port A
J3 J18 J19 J20 K1
PA[6] A[11] D[13] A[13]/DRA[14] PA[1]
1 1 1 1 1
Input
I/O O I/O O I/O
GPIO port A System byte address Data I/O System byte address / SDRAM address GPIO port A
Low Low Low
Input

K2 K3 K18 K19 K20 L1 L2 L3 L18 L19 L20 M1 M2 M3 M18 M19 M20 N1 N2 N3 N18 N19 N20 P1 P2 P3 P18 P19
PA[2] VDDIO D[14] A[14]/DRA[13] D[15] TXD[1] LEDDRV PA[3] VDDIO D[16] A[16]/DRA[11] RXD[1] CTS PA[0] A[15]/DRA[12] A[17]/DRA[10] nTRST DSR nTEST[1] PHDIN D[17] D[19] A[18]/DRA[9] EINT[3] nEINT[2] DCD D[18] A[20]/DRA[7]
1
Input
I/O Pad power
GPIO port A Digital I/O power, 3.3V Data I/O System byte address / SDRAM address Data I/O UART 1 transmit data out IR LED drive GPIO port A Digital I/O power, 3.3V Data I/O System byte address / SDRAM address UART 1 receive data input UART 1 clear to send input GPIO port A System byte address / SDRAM address System byte address / SDRAM address JTAG async reset input UART 1 data set ready input Test mode select input Photodiode input Data I/O Data I/O System byte address / SDRAM address External interrupt External interrupt input UART 1 data carrier detect Data I/O System byte address / SDRAM address
1 1 1 1 1 1
Low Low Low High Low
I/O O I/O O O I/O Pad power
Input
1 1
Low Low
I/O O I I
1 1 1
Input
I/O O O I I
Low Low
With p/u*
I I
1 1 1
Low Low Low
I/O I/O O I I I
1 1
Low Low
I/O O
(c)
DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
43
EP7312 High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location Name
Strength 1
Reset State Low
Type
Description
P20 R1 R2 R3 R18 R19 R20 T1
D[20] nEXTFIQ PE[2]/CLKSEL nTEST[0] A[19]/DRA[8] D[22] A[21]/DRA[6] PE[1]/BOOTSEL[1]
I/O I
Data I/O External fast interrupt input GPIO port E / clock input mode select Test mode select input System byte address / SDRAM address Data I/O System byte address / SDRAM address GPIO port E / boot mode select
1 With p/u* 1 1 1 1
Input
I/O I
Low Low Low
O I/O O I/O
Input

T2 T3 T18 T19 T20 U1 U2 U3 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16
PE[0]/BOOTSEL[0] nEINT[1] D[21] D[23] A[22]/DRA[5] VSSRTC RTCOUT RTCIN HALFWORD D[24] A[23]/DRA[4] VDDRTC VSSIO VSSIO PD[7]/SDQM[1] PD[4] PD[2] SSICLK SSIRXDA nADCCS VDDIO ADCCLK COL[7] COL[4] TCLK BUZ D[29]
1
Input
I/O I
GPIO port E / boot mode select External interrupt input Data I/O Data I/O System byte address / SDRAM address Real time clock ground Real time clock oscillator output Real time clock oscillator input Halfword access select output Data I/O System byte address / SDRAM address Real time clock power, 2.5V I/O ground I/O ground GPIO port D / SDRAM byte lane mask GPIO port D GPIO port D DAI/CODEC/SSI2 serial clock DAI/CODEC/SSI2 serial data input SSI1 ADC chip select Digital I/O power, 3.3V SSI1 ADC serial clock Keyboard scanner column drive Keyboard scanner column drive JTAG clock Buzzer drive output Data I/O
1 1 1
Low Low Low
I/O I/O O RTC ground O I/O
1 1 1
Low Low Low
O I/O O RTC power Pad ground Pad ground
1 1 1 1
Low Low Low
I/O I/O I/O I/O I/O
Input
1
High
O Pad power
1 1 1
Low High High
O O O I
1 1
Low Low
O I/O
(c)
44
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location Name
Strength 2
Reset State Low
Type
Description
V17 V18
A[26]/DRA[1] VDDIO
O Pad power
System byte address / SDRAM address Digital I/O power, 3.3 V Digital I/O power, 3.3 V System byte address / SDRAM address I/O ground I/O ground I/O ground GPIO port D / SDRAM byte lane mask JTAG mode select GPIO port D DAI/CODEC/SSI2 frame sync DAI/CODEC/SSI2 frame sync Core Ground
V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9
VDDIO A[24]/DRA[3] VSSIO VSSIO VSSIO PD[6]/SDQM[0] TMS PD[1] SSITXFR SSIRXFR VSSCORE High / Low Low 1 with p/u* 1 1 1 Low Low Low ` Low
Pad power O Pad ground Pad ground Pad ground I/O I I/O I/O I/O Core Ground
Input
W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10
DRIVE[1] ADCOUT FB[0] COL[5] COL[2] COL[0] D[30] A[27]/DRA[0] D[26] VDDIO D[25] VSSIO VSSIO VSSIO PD[5] PD[3] PD[0]/LEDFLSH SSITXDA ADCIN VDDCORE DRIVE[0]
2 1
I/O O I
PWM drive output SSI1 ADC serial data output PWM feedback input Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Data I/O System byte address / SDRAM address Data I/O Digital I/O power, 3.3V Data I/O I/O ground I/O ground I/O ground GPIO port D GPIO port D GPIO port D / LED blinker output DAI/CODEC/SSI2 serial data output SSI1 ADC serial input Digital core power, 2.5V PWM drive output
1 1 1 1 2 1
High High High Low Low Low
O O O I/O O I/O Pad power
1
Low
I/O Pad ground Pad ground Pad ground
1 1 1 1
Low Low Low Low
I/O I/O I/O O I Core power
2
Input
I/O
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DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
45
EP7312 High-Performance, Low-Power System on Chip
Table 21. 204-Ball TFBGA Ball Listing (Continued)
Ball Location Name
Strength 1
Reset State Low
Type
Description
Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20
SMPCLK FB[1] COL[6] COL[3] COL[1] D[31] D[28] D[27] A[25]/DRA[2] VDDIO
O I
SSI1 ADC sample clock PWM feedback input Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Data I/O Data I/O Data I/O System byte address / SDRAM address Digital I/O power, 3.3V
1 1 1 1 1 1 2
High High High Low Low Low Low
O O O I/O I/O I/O O Pad power
*"With p/u" means with internal pull-up of 100 KOhms on the pin.
Strength 1 = 4 ma Strength 2 = 12 ma
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
256-Ball PBGA Package Characteristics
Figure 18. 256-Ball PBGA Package Note: 1) For pin locations see Table 22. 2) Dimensions are in millimeters (inches), and controlling dimension is millimeter 3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information.
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46
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
0.85 (0.034) 0.05 (.002) 17.00 (0.669) 0.20 (.008) Pin 1 Corner 15.00 (0.590) 0.20 (.008) 30 TYP 0.40 (0.016) 0.05 (.002)
D1
Pin 1 Indicator 17.00 (0.669) 0.20 (.008)
E1
15.00 (0.590) 0.20 (.008)
2 Layer 0.36 (0.014) 0.09 (0.004)
TOP VIEW
SIDE VIEW
D
17.00 (0.669) 1.00 (0.040) 1.00 (0.040) REF
16 15 14 13 12 11 10 9 8 7
Pin 1 Corner
E
65 432 1
1.00 (0.040) REF
1.00 (0.040)
A B C D E F G H J K L M N P R T
BOTTOM VIEW
17.00 (0.669)
0.50 R 3 Places
JEDEC #: MO-151 Ball Diameter: 0.50 mm 0.10 mm 17 17 1.61 mm body
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DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
47
EP7312 High-Performance, Low-Power System on Chip
256-Ball PBGA Pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A
VDDIO
nCS[4]
nCS[1]
SDCLK nMOE/ nSDCAS
SDQM[3]
DD[1]
M
VDDIO
D[0]
D[2]
A[3]
VDDIO
A[6]
MOSCOUT
VDDOSC
VSSIO
A
B
nCS[5]
VDDIO
nCS[3]
VDDIO
nSDCS[1]
DD[2]
CL[1]
VDDCORE
D[1]
A[2]
A[4]
A[5]
WAKEUP
VDDIO
nURESET
B
C
VDDIO WRITE/ nSDRAS
EXPCLK
VSSIO
VDDIO
VSSIO
VSSIO nMWE/ nSDWE
VSSIO
VDDIO
VSSIO
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
nPOR
nEXTPWR C
D
EXPRDY
VSSIO
VDDIO
nCS[2]
nSDCS[0]
CL[2]
VSSRTC
D[4]
nPWRFL
MOSCIN
VDDIO nMEDCHG/ nBROM
VSSIO
D[7]
D[8]
D
E
RXD[2]
PB[7]
TDI
WORD
VSSIO RUN/ CLKEN
nCS[0]
SDQM[2]
FRM
A[0]
D[5]
VSSOSC
VSSIO
VDDIO
D[9]
D[10]
E
F
PB[5]
PB[3]
VSSIO
TXD[2]
VSSIO
SDCKE
DD[3]
A[1]
D[6]
VSSRTC
BATOK
nBATCHG
VSSIO
D[11]
VDDIO
F
G
PB[1]
VDDIO
TDO
PB[4]
PB[6]
VSSCore
VSSRTC
DD[0]
D[3]
VSSRTC
A[7]
A[8]
A[9] A[13]/ DRA[14] A[14]/ DRA[13]
VSSIO
D[12]
D[13]
G
H
PA[7]
PA[5]
VSSIO
PA[4]
PA[6]
PB[0]
PB[2]
VSSRTC
VSSRTC
A[10] A[17]/ DRA[10]
A[11] A[16]/ DRA[11]
A[12] A[15]/ DRA[12]
VSSIO
D[14]
D[15]
H
J
PA[3]
PA[1]
VSSIO
PA[2]
PA[0]
TXD[1]
CTS
VSSRTC
VSSRTC
nTRST
D[16]
D[17]
J
K
LEDDRV
PHDIN
VSSIO
DCD
nTEST[1] PE[2]/ CLKSEL
EINT[3]
VSSRTC PD[0]/ LEDFLSH
ADCIN
COL[4]
TCLK
D[20]
D[19] A[22]/ DRA[5]
D[18] A[21]/ DRA[6] A[23]/ DRA[4]
VSSIO
VDDIO A[18]/ DRA[9] A[20]/ DRA[7]
VDDIO A[19]/ DRA[8]
K
L
RXD[1]
DSR
VDDIO
nEINT[1] PE[0]/ BOOTSEL[0]
VSSRTC
VSSRTC
COL[6]
D[31]
VSSRTC
VSSIO
L
M nTEST[0]
nEINT[2] PE[1]/ BOOTSEL[1]
VDDIO
TMS
VDDIO
SSITXFR
DRIVE[1]
FB[0]
COL[0]
D[27]
VSSIO
VDDIO
D[21]
M
N
nEXTFIQ
VSSIO
VDDIO
PD[5]
PD[2]
SSIRXDA
ADCCLK
SMPCLK
COL[2]
D[29]
D[26]
HALFWORD
VSSIO
D[22]
D[23]
N
P
VSSRTC
RTCOUT
VSSIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO
VSSIO
VDDIO
VSSIO
VSSIO
VDDIO A[27]/ DRA[0]
VSSIO A[25]/ DRA[2] A[26]/ DRA[1]
D[24]
VDDIO A[24]\ DRA[3]
P
R
RTCIN
VDDIO PD[7]/ SDQM[1]
PD[4] PD[6]/ SDQM[0]
PD[1]
SSITXDA
nADCCS
VDDIO
ADCOUT
COL[7]
COL[3]
COL[1]
D[30]
VDDIO
R
T
VDDRTC
PD[3]
SSICLK
SSIRXFR
VDDCORE
DRIVE[0]
FB[1]
COL[5]
VDDIO
BUZ
D[28]
D[25]
VSSIO
T
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48
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
256-Ball PBGA Ball Listing
The list is ordered by ball location.
Table 22. 256-Ball PBGA Ball Listing
Ball Location A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 Name VDDIO nCS[4] nCS[1] SDCLK SDQM[3] DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO nCS[5] VDDIO nCS[3] nMOE/nSDCAS VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO 1 Schmitt 1 2 1 1 Schmitt Low Low Low Low 1 1 1 High Low Low 1 1 High High 1 Low 1 Low 1 1 2 Low Low Low 1 1 2 2 1 1 High High Low Low Low Low Strength
Reset State
Type Pad power O O O O O O Pad power I/O I/O O Pad power O O Oscillator power Pad ground O Pad power O O Pad power O O O Core power I/O O O O I Pad power I Pad power I Pad ground Pad power Pad ground Pad ground Pad ground Pad power Pad ground Pad ground Pad ground Pad power Pad ground Digital I/O power, 3.3 V Chip select 4 Chip select 1 SDRAM clock out SDRAM byte lane mask LCD serial display data LCD AC bias drive Digital I/O power, 3.3 V Data I/O Data I/O System byte address Digital I/O power, 3.3V System byte address Main oscillator out Oscillator power in, 2.5 V I/O ground Chip select 5 Digital I/O power, 3.3 V Chip select 3
Description
ROM, expansion OP enable/SDRAM CAS control signal Digital I/O power, 3.3 V SDRAM chip select 1 LCD serial display data LCD line clock Digital core power, 2.5V Data I/O System byte address System byte address System byte address System wake up input Digital I/O power, 3.3 V User reset input Digital I/O power, 3.3V Expansion clock input I/O ground Digital I/O power, 3.3 V I/O ground I/O ground I/O ground Digital I/O power, 3.3 V I/O ground I/O ground I/O ground Digital I/O power, 3.3 V I/O ground
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DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
49
EP7312 High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Ball Location C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 Name VSSIO nPOR nEXTPWR WRITE/nSDRAS EXPRDY VSSIO VDDIO nCS[2] nMWE/nSDWE nSDCS[0] CL[2] VSSRTC D[4] nPWRFL MOSCIN VDDIO VSSIO D[7] D[8] RXD[2] PB[7] TDI WORD VSSIO nCS[0] SDQM[2] FRM A[0] D[5] VSSOSC VSSIO nMEDCHG/nBROM VDDIO D[9] D[10] PB[5] PB[3] VSSIO TXD[2] RUN/CLKEN VSSIO SDCKE DD[3] A[1] D[6] VSSRTC BATOK 2 1 2 1 Low Low Low Low 1 1 High Low 1 1 1 1 Low Low Input Input 1 2 1 2 1 High Low Low Low Low 1 with p/u* 1 Low Input 1 1 Low Low 1 Low 1 1 1 1 High High High Low 1 1 Low Schmitt Strength
Reset State
Type Pad ground I I O I Pad ground Pad power O O O O Core ground I/O I I Pad power Pad ground I/O I/O I I/O ground Power-on reset input External power supply sense input
Description
Transfer direction / SDRAM RAS signal output Expansion port ready input I/O ground Digital I/O power, 3.3V Chip select 2 ROM, expansion write enable/ SDRAM write enable control signal SDRAM chip select 2 LCD pixel clock out Real time clock ground Data I/O Power fail sense input Main oscillator input Digital I/O power, 3.3V I/O ground Data I/O Data I/O UART 2 receive data input GPIO port B JTAG data input Word access select output I/O ground Chip select 0 SDRAM byte lane mask LCD frame synchronization pulse System byte address Data I/O PLL ground I/O ground Media change interrupt input / internal ROM boot enable Digital I/O power, 3.3V Data I/O Data I/O GPIO port B GPIO port B I/O ground UART 2 transmit data output Run output / clock enable output I/O ground SDRAM clock enable output LCD serial display data System byte address Data I/O Real time clock ground Battery OK input
I I O Pad ground O O O O I/O Oscillator ground Pad ground I Pad power I/O I/O I I Pad ground O O Pad ground O O O I/O RTC ground I

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50
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Ball Location F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 J2 J3 J4 J5 J6 Name nBATCHG VSSIO D[11] VDDIO PB[1] VDDIO TDO PB[4] PB[6] VSSCore VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] PA[7] PA[5] VSSIO PA[4] PA[6] PB[0] PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13]/DRA[14] VSSIO D[14] D[15] PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] 1 1 1 Input Input 1 1 1 1 Low Low Input Input 1 1 1 1 Low Low Low Low 1 1 1 1 Input Input Input Input 1 1 1 1 Low Low Input Input 1 1 1 Low Low Low 1 1 Low Low 1 1 1 Input Input Input 1 Input 1 Low Strength
Reset State
Type I Pad ground I/O Pad power Battery changed sense input I/O ground Data I/O Digital I/O power, 3.3V GPIO port B Digital I/O power, 3.3V JTAG data out GPIO port B GPIO port B Core ground Real time clock ground LCD serial display data Data I/O Real time clock ground System byte address System byte address System byte address I/O ground Data I/O Data I/O GPIO port A GPIO port A I/O ground GPIO port A GPIO port A GPIO port B GPIO port B Real time clock ground Real time clock ground System byte address System byte address System byte address
Description
I Pad power

O I I Core ground RTC ground O I/O RTC ground O O O Pad ground I/O I/O I/O I/O Pad ground

I/O I/O I/O I/O RTC ground RTC ground O O O O Pad ground I/O I/O I/O I/O Pad ground
System byte address / SDRAM address I/O ground Data I/O Data I/O GPIO port A GPIO port A I/O ground GPIO port A GPIO port A UART 1 transmit data out

I/O I/O O
High
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DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
51
EP7312 High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Ball Location J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 M1 M2 M3 M4 M5 Name CTS VSSRTC VSSRTC A[17]/DRA[10] A[16]/DRA[11] A[15]/DRA[12] A[14]/DRA[13] nTRST D[16] D[17] LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO RXD[1] DSR VDDIO nEINT[1] PE[2]/CLKSEL VSSRTC PD[0]/LEDFLSH VSSRTC COL[6] D[31] VSSRTC A[22]/DRA[5] A[21]/DRA[6] VSSIO A[18]/DRA[9] A[19]/DRA[8] nTEST[0] nEINT[2] VDDIO PE[0]/BOOTSEL[0] TMS 1 with p/u* Input 1 1 With p/u* Low Low 1 1 Low Low 1 1 High Low 1 Low 1 Input 1 1 1 Low Low Low 1 High With p/u* 1 1 1 Low Low Low 1 1 1 1 Low Low Low Low Strength
Reset State
Type I RTC ground RTC ground O O O O I I/O I/O O I Pad ground I I I RTC ground I O I I/O I/O I/O Pad ground Pad power Pad power I I Pad power I UART 1 clear to send input Real time clock ground Real time clock ground
Description
System byte address / SDRAM address System byte address / SDRAM address System byte address / SDRAM address System byte address / SDRAM address JTAG async reset input Data I/O Data I/O IR LED drive Photodiode input I/O ground UART 1 data carrier detect Test mode select input External interrupt Real time clock ground SSI1 ADC serial input Keyboard scanner column drive JTAG clock Data I/O Data I/O Data I/O I/O ground Digital I/O power, 3.3V Digital I/O power, 3.3V UART 1 receive data input UART 1 data set ready input Digital I/O power, 3.3V External interrupt input GPIO port E / clock input mode select Real time clock ground GPIO port D / LED blinker output Real time clock ground Keyboard scanner column drive Data I/O Real time clock ground System byte address / SDRAM address System byte address / SDRAM address I/O ground System byte address / SDRAM address System byte address / SDRAM address Test mode select input External interrupt input Digital I/O power, 3.3V GPIO port E / Boot mode select JTAG mode select
I/O RTC ground I/O Core ground O I/O RTC ground O O Pad ground O O I I Pad power
I I
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52
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Ball Location M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 Name VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO A[23]/DRA[4] VDDIO A[20]/DRA[7] D[21] nEXTFIQ PE[1]/BOOTSEL[1] VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23] VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO D[24] VDDIO RTCIN VDDIO PD[4] PD[1] 1 1 Low Low 1 Low 1 1 Low Low 1 1 1 1 1 1 Low Low High Low Low Low 1 1 Low Low 1 Input 1 1 Low Low 1 Low 1 1 High Low 1 2 Low High / Low Strength
Reset State
Type Pad power I/O I/O I O I/O Pad ground O Pad power O I/O I Digital I/O power, 3.3V DAI/CODEC/SSI2 frame sync PWM drive output PWM feedback input Keyboard scanner column drive Data I/O I/O ground
Description
System byte address / SDRAM address Digital I/O power, 3.3V System byte address / SDRAM address Data I/O External fast interrupt input GPIO port E / boot mode select I/O ground Digital I/O power, 3.3V GPIO port D GPIO port D DAI/CODEC/SSI2 serial data input SSI1 ADC serial clock SSI1 ADC sample clock Keyboard scanner column drive Data I/O Data I/O Halfword access select output I/O ground Data I/O Data I/O Real time clock ground Real time clock oscillator output I/O ground I/O ground Digital I/O power, 3.3V I/O ground I/O ground Digital I/O power, 3.3V I/O ground Digital I/O power, 3.3V I/O ground I/O ground Digital I/O power I/O ground Data I/O Digital I/O power, 3.3V Real time clock oscillator input Digital I/O power, 3.3V GPIO port D GPIO port D
I/O Pad ground Pad power I/O I/O I/O O O O I/O I/O O Pad ground I/O I/O RTC ground O Pad ground Pad ground Pad power Pad ground Pad ground Pad power Pad ground Pad power Pad ground Pad ground Pad power Pad ground I/O Pad power I/O Pad power I/O I/O
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DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
53
EP7312 High-Performance, Low-Power System on Chip
Table 22. 256-Ball PBGA Ball Listing (Continued)
Ball Location R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Name SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30] A[27]/DRA[0] A[25]/DRA[2] VDDIO A[24]/DRA[3] VDDRTC PD[7]/SDQM[1] PD[6]/SDQM[0] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26]/DRA[1] D[25] VSSIO 1 1 2 1 Low Low Low Low 1 High 2 High / Low 1 1 1 1 1 Low Low Low Input Input 1 Low 1 1 1 1 1 2 2 Low High High High Low Low Low Strength 1 1
Reset State Low High
Type O O Pad power O O O O I/O O O Pad power O RTC power I/O I/O I/O I/O I/O Core power I/O I O Pad power O I/O O I/O Pad ground DAI/CODEC/SSI2 serial data output SSI1 ADC chip select Digital I/O power, 3.3V SSI1 ADC serial data output Keyboard scanner column drive Keyboard scanner column drive Keyboard scanner column drive Data I/O
Description
System byte address / SDRAM address System byte address / SDRAM address Digital I/O power, 3.3V System byte address / SDRAM address Real time clock power, 2.5V GPIO port D / SDRAM byte lane mask GPIO port D / SDRAM byte lane mask GPIO port D DAI/CODEC/SSI2 serial clock DAI/CODEC/SSI2 frame sync Core power, 2.5V PWM drive output PWM feedback input Keyboard scanner column drive Digital I/O power, 3.3V Buzzer drive output Data I/O System byte address / SDRAM address Data I/O I/O ground

*
"With p/u" means with internal pull-up of 100 KOhms on the pin. Strength 1 = 4 ma Strength 2 = 12 ma
Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
JTAG Boundary Scan Signal Ordering
Table 23. JTAG Boundary Scan Signal Ordering
LQFP Pin No.
1 4 5 6 7
TFBGA Ball
B3 A2 B1 E3 C1
PBGA Ball
B1 C2 E4 D1 F5
Signal
nCS[5] EXPCLK WORD WRITE/nSDRAS RUN/CLKEN
Type
O I/O O O O
Position
1 3 6 8 10
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54
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
DS508PP5
EP7312 High-Performance, Low-Power System on Chip
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP Pin No.
8 9 10 13 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 53 54 55
TFBGA Ball
C2 E2 D2 F3 D1 F2 E1 F1 G2 G1 H3 H1 J3 J2 J1 L3 K2 K1 M3 L2 L1 N3 M2 M1 P3 N1 N2 R3 P1 P2 T3 R1 R2 T1 T2 V4 W4 Y4
PBGA Ball
D2 F4 E1 E2 G5 F1 G4 F2 H7 G1 H6 H1 H5 H2 H4 J1 J4 J2 J5 K1 J6 K2 J7 L1 K4 L2 K5 M1 K6 M2 L4 N1 L5 N2 M4 T2 T3 N5
Signal
EXPRDY TXD2 RXD2 PB[7] PB[6] PB[5] PB[4] PB[3] PB[2] PB[1] PB[0] PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] LEDDRV TXD1 PHDIN CTS RXD1 DCD DSR nTEST1 nTEST0 EINT3 nEINT2 nEINT1 nEXTFIQ PE[2]/CLKSEL PE[1]/ BOOTSEL[1] PE[0]/BOOTSEL0 PD[7]/SDQM[1] PD[6/SDQM[0]] PD[5]
Type
I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I I I I I I I I I I I I/O I/O I/O I/O I/O I/O
Position
13 14 16 17 20 23 26 29 32 35 38 41 44 47 50 53 56 59 62 65 67 69 70 71 72 73 74 75 76 77 78 79 80 83 86 89 92 95
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DS508PP5
Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
55
EP7312 High-Performance, Low-Power System on Chip
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP Pin No.
56 59 60 61 62 68 69 70 75 76 77 78 79 80 82 83 84 85 86 87 88 91 92 93 94 95 96 97 99 100 101 102 103 104 105 106 109 110
TFBGA Ball
V5 Y5 V6 W6 Y6 W8 Y8 V9 W10 Y10 V11 W11 Y11 Y12 Y11 Y12 Y13 W13 V13 Y14 W14 Y15 W15 V15 Y16 W16 V16 Y17 Y16 Y18 V17 W18 Y19 Y20 U18 V209 U19 U20
PBGA Ball
R3 T4 N6 R4 L7 T6 K8 R6 M8 T8 N8 R8 N9 T9 M9 R9 L9 T10 K9 R10 N10 R11 M10 T12 L10 R12 N11 T13 R13 M11 T14 N12 R14 T15 N13 R16 P15 M13
Signal
PD[4] PD[3] PD[2] PD[1] PD[0]/LEDFLSH SSIRXFR ADCIN nADCCS DRIVE1 DRIVE0 ADCCLK ADCOUT SMPCLK FB1 FB0 COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0 BUZ D[31] D[30] D[29] D[28] A[27]/DRA[0] D[27] A[26]/DRA[1] D[26] A[25]/DRA[2] D[25] HALFWORD A[24]/DRA[3] D[24] A[23]/DRA[4]
Type
I/O I/O I/O I/O O I/O I O I/O I/O O O O I I O O O O O O O O O I/O I/O I/O I/O Out I/O O I/O O I/O O O I/O O
Position
98 101 104 107 110 122 125 126 128 131 134 136 138 140 141 142 144 146 148 150 152 154 156 158 160 163 166 169 172 174 177 179 182 184 187 189 191 194
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Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP Pin No.
111 112 113 114 115 117 118 119 120 121 122 126 127 128 129 130 131 132 133 134 135 136 137 138 141 142 143 144 145 146 147 148 150 151 152 153 154 155
TFBGA Ball
T19 T20 R19 R20 T18 P19 P20 R18 N19 N20 P18 M19 N18 L20 L19 M18 K20 K19 K18 J20 J19 H20 H19 J18 G20 H18 F20 G19 E20 F19 G18 D20 F18 D19 E19 C19 C20 E18
PBGA Ball
N16 L12 N15 L13 M16 M15 K11 L16 K12 L15 K13 J10 J16 J11 J15 J12 H16 J13 H15 H13 G16 H12 G15 H11 F15 H10 E16 G13 E15 G12 D16 G11 D15 F13 C16 F12 C15 E13
Signal
D[23] A[22]/DRA[5] D[22] A[21]/DRA[6] D[21] A[20]/DRA[7] D[20] A[19]/DRA[8] D[19] A[18]/DRA[9] D[18] A[17]/DRA[10] D[17] A[16]/DRA[11] D[16] A[15]/DRA[12] D[15] A[14]/DRA[13] D[14] A[13]/DRA[14] D[13] A[12] D[12] A[11] D[11] A[10] D[10] A[9] D[9] A[8] D[8] A[7] D[7] nBATCHG nEXTPWR BATOK nPOR nMEDCHG/nBROM
Type
I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O O I/O I I I I I
Position
196 199 201 204 206 209 211 214 216 219 221 224 226 229 231 234 236 239 241 244 246 249 251 254 256 259 261 264 266 269 271 274 276 279 280 281 282 283
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EP7312 High-Performance, Low-Power System on Chip
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
LQFP Pin No.
156 161 162 163 164 165 166 169 170 171 172 173 175 176 177 178 179 184 185 186 187 188 189 191 192 193 194 195 196 199 200 201 202 204 205 206 207 208
TFBGA Ball
B20 B16 A16 C15 B15 A15 C14 B14 A14 C13 B13 A13 C12 B12 A12 C11 B11 B10 A10 A9 B9 C9 A8 B8 C8 A7 B7 C7 A6 B6 C6 A5 B5 C5 A4 B4 A3 C4
PBGA Ball
B16 B14 D11 A13 F10 B13 E10 B12 D10 A11 G9 B11 A10 F9 B10 E9 A9 D8 B8 E8 A7 F8 B7 A6 G8 B6 D7 A5 E7 F7 A4 D6 B4 E6 A3 D5 B3 A2
Signal
nURESET WAKEUP nPWRFL A[6] D[6] A[5] D[5] A[4] D[4] A[3] D[3] A[2] D[2] A[1] D[1] A[0] D[0] CL2 CL1 FRM M DD[3] DD[2] DD[1] DD[0] nSDCS[1] nSDCS[0] SDQM[3] SDQM[2] SDCKE SDCLK nMWE/nSDWE nMOE/nSDCAS nCS[0] nCS[1] nCS[2] nCS[3] nCS[4]
Type
I I I O I/O O I/O O I/O O I/O O I/O O I/O O I/O O O O O O O O O O O I/O I/O I/O I/O O O O O O O O
Position
284 285 286 287 289 292 294 297 299 302 304 307 309 312 314 317 319 322 324 326 328 330 333 336 339 342 344 346 349 352 355 358 360 362 364 366 368 370
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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved)
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EP7312 High-Performance, Low-Power System on Chip
1) See EP7312 Users' Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable.
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EP7312 High-Performance, Low-Power System on Chip
CONVENTIONS
This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet.
Table 24. Acronyms and Abbreviations (Continued)
Acronym/ Abbreviation
TAP TLB
Definition
test access port translation lookaside buffer universal asynchronous receiver
Acronyms and Abbreviations
Table 24 lists abbreviations and acronyms used in this data sheet.
Table 24. Acronyms and Abbreviations
UART
Units of Measurement
Table 25. Unit of Measurement
Acronym/ Abbreviation
A/D ADC CODEC D/A DMA EPB FCS FIFO FIQ GPIO ICT IR IRQ IrDA JTAG LCD LED LQFP LSB MIPS MMU MSB PBGA PCB PDA PLL p/u RISC RTC SIR SRAM SSI
Definition
analog-to-digital analog-to-digital converter coder / decoder digital-to-analog direct-memory access embedded peripheral bus frame check sequence first in / first out fast interrupt request general purpose I/O in circuit test infrared standard interrupt request Infrared Data Association Joint Test Action Group liquid crystal display light-emitting diode low profile quad flat pack least significant bit millions of instructions per second memory management unit most significant bit plastic ball grid array printed circuit board personal digital assistant phase locked loop pull-up resistor reduced instruction set computer Real-Time Clock slow (9600-115.2 kbps) infrared static random access memory synchronous serial interface
Symbol
Unit of Measure
degree Celsius sample frequency hertz (cycle per second) kilobits per second kilobyte (1,024 bytes) kilohertz kilo Ohm megabits (1,048,576 bits) per second megabyte (1,048,576 bytes) megabytes per second megahertz (1,000 kilohertz) microampere microfarad microwatt microsecond (1,000 nanoseconds) milliampere milliwatt millisecond (1,000 microseconds) nanosecond volt watt
C
fs Hz kbps KB kHz k Mbps MB MBps MHz A F W s mA mW ms ns V W
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General Conventions
Hexadecimal numbers are presented with all letters in uppercase and a lowercase "h" appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, `11' designates a binary number). Numbers not indicated by an "h", 0x or quotation marks are decimal. Registers are referred to by acronym, with bits listed in brackets separated by a colon (:) (for example, CODR[7:0]), and are described in the EP7312 User's Manual. The use of "TBD" indicates values that are "to be determined," "n/a" designates "not available," and "n/c" indicates a pin that is a "no connect."
Pin Description Conventions
Abbreviations used for signal directions are listed in Table 26.
Table 26. Pin Description Conventions
Abbreviation
I O I/O Input Output Input or Output
Direction
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Ordering Information
The following EP7312 devices are available: -- -- -- -- -- -- EP7312-CV EP7312-CB EP7312-CV-90 EP7312-CR-90 EP7312-IR EP7312-IB-90 -- EP7312-IV -- EP7312-CR -- EP7312-CB-90 -- EP7312-IB -- EP7312-IV-90 -- EP7312-IR-90
Ordering Information Legend
.
EP7312 -- CV --XX
Processor Speed Package Type: V = Low Profile Quad Flat Pack (208-pin LQFP) B = Plastic Ball Grid Array (17 mm x 17 mm) (256-ball PBGA) R = Reduced Ball Grid Array (13 mm x 13 mm) (204-pin TFBGA) Part Number Product Line: Embedded Processor Temperature Range: C = Commercial E = Extended Operating Version I = Industrial Operating Version
Note:
Go to the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative.
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EP7312 High-Performance, Low-Power System on Chip
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
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